1. Technical Field
This invention generally pertains to semiconductor packaging, and more particularly, to using an interposer in leadframe semiconductor packages having multiple, stacked dies for enhanced electrical interconnections and signal routing between the dies and the leads of the package.
2. Related Art
A demand for electronic devices that are smaller and lighter, yet more functional, has resulted in a concomitant demand for semiconductor packages that have smaller outlines and mounting footprints, yet which are capable of increased component packaging densities. One approach to satisfying this demand has been the development of techniques for stacking the semiconductor dies, or xe2x80x9cchips,xe2x80x9d contained in the package on top of one another. Examples of die-stacking techniques may be found, for example, in U.S. Pat. Nos. 5,323,060 and 5,721,452 to R. Fogel, et al.; U.S. Pat. No. 5,815,372 to W. N. Gallas; U.S. Pat. No. 5,898,220 and U.S. Pat. No. Re. 36,613 to M. B. Ball.
A common problem experienced with packages containing multiple dies, and particularly in leadframe types of packages, is the paucity of internal electrical interconnections and signal routings possible between the dies themselves, and between the dies and the input/output terminals of the package. In the case of leadframe packages, these terminals consist of the leads of the leadframe, which may be relatively few in comparison with the number of wire bonding pads on the dies. Thus, the packaging of multiple dies in a leadframe package format has typically been limited to a simple xe2x80x9cfan-outxe2x80x9d interconnection of the dies to the leads, with very limited die-to-die interconnection and signal routing capability. Multiple-die packages requiring a more complex die-to-die interconnection and routing capabilities have typically been implemented in relatively more expensive, laminate-based packages, e.g., Ball Grid Array (xe2x80x9cBGAxe2x80x9d) packages.
A need therefore exists for a simple, low-cost method of enhancing the number and efficiency of internal electrical interconnectability and signal routing between the dies, and between the dies and the leads, of a leadframe type of semiconductor package having multiple, stacked dies.
This invention provides method for enhancing the internal electrical interconnectability and signal routing between the dies and leads of a leadframe type of semiconductor package having multiple, stacked dies. The novel package of the invention includes a conventional metallic leadframe having a plurality of leads arrayed along the sides of a die paddle. A plurality of semiconductor dies, each having wire bonding pads arrayed around a periphery of the active surface thereof, are laminated in a stack with the die paddle of the leadframe, and optionally, with a spacer for spacing the dies apart in the stack.
Advantageously, an xe2x80x9cinterposerxe2x80x9d is also laminated in the stack along with the dies and the die paddle. The interposer comprises at least one dielectric layer and at least one metallic layer that has been patterned to include a plurality of wire bonding pads arrayed around a periphery of a surface thereof, and a plurality of circuit traces interconnecting selected ones of the wire bonding pads across the span of the interposer.
A plurality of conventional wire bonds are made between selected ones of the die bonding pads, the interposer bonding pads, and the leads of the leadframe to electrically interconnect the package internally. The bonding pads and circuit traces, all of which lie in a single plane, can be simply and flexibly prearranged on the interposer to increase the number of internal electrical interconnections and signal routings otherwise possible between the dies and the leads of the package, which necessarily reside in multiple and different planes, and on different sides of the package.